Session 11B1 NMOS Realization Of Ternery Functions With Digital Summation Threshold Gates
نویسنده
چکیده
An NMOS circuit realization is proposed for ternary functions based on a digital summation threshold gate. The procedure is systematic and any ternary function can be realized with a single gate. Many ternary functions were realized and the resulting circuits were simulated using the MCNC ( Microelectronics Center for North Carolina ) tools for VLSI design. The speed and complexity of the gate depends on the weighted sum for a given function.
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تاریخ انتشار 2004